As medical equipment becomes more advanced, the demands on the electronic components are increasing exponentially. Large amounts of data are being collected during various tasks and systems need to be able to handle it. This article reviews one effort to alleviate these concerns with the introduction of PCI Express.
By Paul Gaudreau
AT A GLANCE
Shared multi-drop buses such as PCI (peripheral component interconnect) and CompactPCI are giving way to point-to-point interfaces such as PCI Express and CompactPCI Express as a way of handling more data traffic more quickly. This transition will be especially important in medical diagnostic equipment, where greater volumes of imaging data threaten to overwhelm and bog the system down.
Since its advent in the early 1990s, the PCI bus has become the mainstay of embedded computing, including PC- and server-based medical equipment, but its capabilities are now being stretched to the breaking point. Leading-edge medical diagnostic equipment, for example, is capturing more and more data, creating a heavier processing burden and the need for higher data rates. A bus can quickly become saturated, bogging the equipment down. The same is true in other areas, such as geophysical imaging and a number of military/aerospace applications.The solution to the bus bottleneck, now gaining a foothold in commercial computers, is PCI Express—a point-to-point, switch-oriented interface boasting high speed and an architecture that avoids the contention for shared bus resources that can kill performance. Just as its predecessor PCI was adapted for a variety of form factors to suit different application needs, PCI Express is also becoming available in numerous incarnations.
Open-architecture system buses have evolved over the past 30 years to accommodate faster and faster microprocessors on the one hand, and ever speedier I/O interfaces on the other. The 5 to 10 MHz signaling frequencies of early buses, for example, gave way to 33 MHz with the advent of PCI in 1992, 66 MHz with the birth of AGP (accelerated graphics port) in 1996, and 133 MHz with the PCI-X specification introduction in 1999. These parallel buses have also expanded the width of their data buses to speed operation, with the 8-bit STD bus growing to 16 bits and then 32 bits, for example, and the VMEbus expanding from 32 to 64 bits.
But buses have their limits. Making a bus faster or wider has inevitable consequences for such issues as crosstalk, ground bounce, and skew. Moreover, the more boards there are on a bus, the less bandwidth there is available for each individual board. Further, since a bus is a shared system resource which only one board can make use of at one time, boards must arbitrate to gain access to the bus. This introduces latency into a transaction and worse, unless a system is carefully crafted, some boards may not be able to acquire the bus when they need to.Nevertheless, buses are quite adequate for most applications. And where system requirements might strain the bus, it’s possible to offload certain kinds of traffic to auxiliary buses. In the early days of PCI, for example, graphics traffic was offloaded from the ISA (industry standard architecture) bus to PCI; and in later days, as PCI took over most I/O functions, graphics traffic was offloaded from PCI to an auxiliary AGP bus. Most recently, the graphics traffic that previously traveled over the parallel AGP bus is being relegated to a serial point-to-point interface: PCI Express.
From Bus to Point-to-Point Interconnect
PCI Express adopts the PCI software model, simplifying upgrades from the old to the new, but otherwise, the two interfaces differ significantly (Table 1). Whereas PCI is parallel, for example, PCI Express is serial, eliminating the risk of electrical perturbations that can occur on a parallel bus. In addition, whereas PCI is a synchronous bus, with every transaction timed in tune with a centralized clock, PCI Express provides an embedded clock function through its use of 8B/10B encoding. Also, PCI utilizes single-ended signaling, while PCI Express makes use of differential signaling. In the former, a voltage level or transition on one line indicates a digital 0 or 1. In the latter, it’s the difference between the voltages on two lines that defines the signal state. |
In a bus such as PCI, all bus devices interface to a common communications highway, formed by electrical traces or “lines” resident on the motherboard in a traditional PC system or on the backplane of an industrial computer. In contrast, in a point-to-point interface such as PCI Express, devices communicate only with nearest neighbor devices, which have mechanisms for forwarding communications when the intended recipient is further down the highway. Each step between the sender and recipient (traveling through as many neighbor devices as required) is known as a hop. The point-to-point interfaces are oriented towards switched configurations, in which switches provide links to four, six, or more devices, providing shortcuts for communications between any two devices.
Traditional parallel buses contain address lines which all devices monitor, and when the intended recipient recognizes its own range of addresses on these lines, it accepts the transaction—for example, responding to a message, providing requested data, or performing an action it has been commanded to perform. In contrast, the new crop of serial point-to-point interfaces embeds destination addresses within packets, not over a set of dedicated lines. Packets also serve to define other functions for which buses typically provide dedicated lines, such as interrupts and acknowledgements. In a bus, transaction types—reads, writes, etc.—are defined by the states of a particular combination of lines, while in a point-to-point interface, packet codes perform this role.
But perhaps the most important difference between the buses and point-to-point interfaces is that the latter are fast. Very fast. In its maximum configuration—64 bits wide and with a 66 MHz signaling frequency—the PCI bus provides a data rate of 528 Mbytes-per-second (MBPS). This maximum PCI configuration requires a minimum of 47 signal lines, 49 lines for a bus master.
A single PCI Express lane (called an x1 or “by one” configuration) provides a rate of 2.5 Gigabits-per-second (Gbps)—roughly 312 MBPS—at the entry-level 2.5 GHz operating frequency. When both input and output sides of a device are operating simultaneously, that rises to 625 MBPS. The use of 8B/10B encoding exacts a 20% penalty on PCI Express, with the requirement for 10 bits to represent each 8-bit byte. The effective data rate for an x1 configuration is, thus, reduced from 312 to 250 MBPS unidirectionally and from 625 to 500 MBPS bidirectionally. That’s for the minimum PCI Express configuration, which requires a mere six signal lines.
PCI Express is extremely scaleable beyond x1 to x2, x4, x8, x16, and x32 configurations, boosting data rates to as high as 160 Gbps (16 GBPS net) unidirectionally, 320 Gbps (32 GBPS net) bidirectionally. And a second generation of PCI Express silicon is expected soon, doubling the 2.5/5 GHz unidirectional/bidirectional data transfer rate to 5/10 GHz.
The Incarnations of PCI and PCI Express
The popularity of the PCI bus in desktop computers motivated the creation of a whole range of variations, logically and electrically compatible with PCI but adopting new mechanical identities for different environments and requirements (Table 2). Within two years of its appearance, for example, the PICMG (PCI Industrial Computer Manufacturers Association) had developed a passive-backplane variation of PCI for industrial computing and other embedded applications. |
| IEEE: Institute of Electrical and Electronics Engineers PCI-SIG: Peripheral Component Interconnect Special Interest Group PCMCIA: PC Memory card International Association PICMG: PCI Industrial Computer Manufacturers Association VITA: VME International Trade Association |
The PCI specification is based on the motherboard concept. Here, all the essential computer components—the microprocessor CPU, memory, and some I/O devices—reside on a single “system” or “mother” board, which also contains connectors for adding functions by means of smaller plug-in “daughter” boards. With a passive backplane, in contrast, the main board contains no active circuitry at all, serving only as a way for plug-in boards to communicate with each other. The computer resides on a plug-in board and it’s possible to have multiple processing boards.The passive backplane is more serviceable than the motherboard. With the former, system problems or breakdowns can typically be handled by removing a board and plugging-in a replacement. Servicing a problem motherboard, in contrast, requires the computer to be completely disassembled. In embedded applications, it’s more typical to just disconnect the computer and replace it with another before motherboard servicing is attempted.
Both the traditional PCI motherboard system and PICMG industrial PCI systems utilize edge-card connectors for their plug-in boards; an alternative connector scheme is used in another PCI incarnation higher up the reliability ladder. Pin-and-socket connectors are the norm in heavy-duty industrial buses such as VME, and CompactPCI brings that tradition to the PCI-compatible realm.
Pin-and-socket connectors are far more tolerant of shock and vibration than edge-card connectors, and in certain incarnations are effectively sealed against contaminants—even gas. CompactPCI goes a step further, giving up the standard “DIN” connectors in favor of the far denser “2-mm” connectors traditionally used in the telecommunications industry.
Elsewhere, other variations of PCI were developed—for user-accessible cards in laptop computers, for example, for a number of mezzanine bus structures and for severely space-constrained applications. For example, the PC/104 Consortium upgraded its ISA-compatible PC/104 board to the backwards-compatible PC/104-Plus, which integrates both ISA and PCI buses. And the PCMCIA (Personal Computer Memory Card International Association) upgraded its PC Card spec to CardBus, compatible with PCI.
Like the heavy-duty industrial buses before it, CompactPCI provides a choice of add-in board form factors: 3U (single high) and 6U (double high), both 160 mm wide. The 3U (100 mm) boards take up about 15.5 square inches; 6U (233.35 mm) boards, over 37 square inches. By reason of economy, space efficiency, and ruggedness, 3U CompactPCI is the preferred form factor.
PCI Express: Shadowing the PCI Bus
The PCI Express point-to-point interface is likely to become as popular as PCI has been, and it has already spawned a number of its own variations (Table 3), most of them corresponding to previous PCI variations. The PCMCIA group, for instance, has adopted PCI Express in its Express Card specification, which provides both a PCI Express interface and USB (universal serial bus) 2.0; while the PCI-SIG has developed the PCI Express Mini Card specification for customizing motherboards. And for the high-reliability computing sector, PICMG brought forth CompactPCI Express.CompactPCI Express adopts the CompactPCI mechanical definition, bringing a rugged industrial form factor to PCI Express. It specifies a shielded, differential connector able to handle 5 GHz signaling rates and providing two or three x4 PCI Express interfaces. A 3U CompactPCI Express switch board accommodates up to three of these connectors; a 6U switch board, up to eight.
Compatibility with CompactPCI is built into the CompactPCI Express specification, and the two types of boards can coexist on the same backplane. This allows equipment manufacturers to use their tried-and-true legacy CompactPCI boards while upgrading to CompactPCI Express where it’s needed. Moreover, in these early days of CompactPCI Express, it provides a way of integrating a function before that function has become available on a merchant CompactPCI Express board. CompactPCI Express even defines what the PICMG specification calls a “hybrid” add-in card slot, which can take either a CompactPCI board or CompactPCI Express board to handle any contingency (Figure 1).
Conclusion
There are many variations of both PCI and PCI Express to handle the gamut of medical equipment needs. For benign operating environments in non-critical applications, for example, motherboard PCI is probably the most suitable alternative; while for extremely space-constrained applications with higher reliability requirements, PC/104-Plus may be the right approach. And for the ultimate in robustness and reliability, CompactPCI hits the mark.But whatever form factor is most appropriate for a particular application, one thing is certain. Over time, analogous variations of PCI Express will find their way into PCI-based embedded systems: initially in combination with (and eventually independent of) some version of PCI. And those will be the high-end systems with both a heavy data handling burden and stringent reliability demands.
ONLINE
For additional information on the technologies and products discussed in this article, see the following websites:
www.inova-computers.com
Paul Gaudreau is president and CEO of Inova Computers Inc., which specializes in robust embedded computers for applications requiring the utmost in reliability. He brings more than 25 years of experience to the embedded computing arena. Gaudreau can be reached at 401-667-7218 or pgaudreau@inova-computers.com.
